1. Field of the Invention
The present invention relates to the field of semiconductor device manufacturing and, more particularly, to a method for depositing a barrier layer on a semiconductor device.
2. Description of Background Art
In a semiconductor integrated circuit (IC), a high integration density, forces an attendant reduction in the size of individual device elements, such as a channel length of a transistor, an interval between active areas, a wiring width, a wiring interval and, in particular, a size of an electrical contact pad. To obtain a low contact resistance in such a reduced-sized contact pad, the contact pad is generally formed using a metal silicide layer.
The metal silicide layer serves as an ohmic layer which serves as a low resistance interface between a silicon substrate and a metal layer formed on the silicon substrate. The metal silicide layer also serves as a diffusion barrier layer between a metal layer and an underlying semiconductor region or between two metals in a multilevel metal system, which prevents the diffusion of two materials in the metal layer and the underlying semiconductor region into each other. The metal silicide layer is comprised of a material, such as titanium silicide (TiSi2) or a Group-VIII silicides, such as PtSi2, PdSi2, CoSi2, NiSi2 etc. In a conventional semiconductor device using a design rule of 0.25 micron or less, titanium silicide or cobalt silicide (CoSi2) is widely used for the metal silicide layers.
Typically, after depositing a refractory metal layer using a sputtering process, a heat treatment, such as a rapid thermal process (RTP) is used to form the metal silicide layer at the interface of the refractory metal layer and the exposed silicon region.
However, as an aspect ratio (i.e., depth vs. surface opening hole diameter) of a contact hole increases, the use of the sputtering method results in poor step coverage against the stepped portion having a higher aspect ratio, including poor coverage at the bottom of the hole. Thus, forming a layer of metal silicide of a sufficient thickness at the bottom of the contact hole is difficult.
In order to overcome the difficulties of the step coverage including at the bottom of the contact hole due to the use of the sputtering method, deposition of an intermediate refractory metal layer using a chemical vapor deposition (CVD) or a plasma-enhanced CVD (PE-CVD) process has been employed, wherein a metal silicide layer is formed simultaneously with the deposition of the refractory metal layer. According to this method, even if the aspect ratio of the contact hole is high, the refractory metal reacts with silicon in the active region to form a silicide without a subsequent annealing process and results in good step coverage in a simplified process.
FIG. 1 illustrates a cross-sectional view of a contact hole in a semiconductor device formed by a method for forming a barrier layer of a semiconductor device using the conventional CVD process. Referring to FIG. 1, a heavily doped region 12, e.g., a P+ well, is formed at a surface portion of a semiconductor substrate 10 through an ion-implantation process. An insulating layer 14 is deposited on the substrate 10 and selectively etched via a photolithographic process to form a contact hole 16 in order to partially expose the heavily doped region 12, e.g., the P+ well. During movement of wafer shown in FIG. 1 to another chamber for subsequent processing, a thin native oxide layer 18 grows on the exposed silicon surface due to exposure to an ambient atmosphere.
Thereafter, a refractory metal layer 20, e.g., a titanium (Ti) layer, is deposited on the sidewall and the bottom of the contact hole 16 and the insulating layer 14 via a CVD or a PE-CVD process. During the deposition, a reaction occurs between silicon and titanium at an interface between the titanium layer 20 and the exposed silicon area 12, whereby a titanium silicide (TiSix) layer is formed. A refractory metal nitride layer, e.g., a titanium nitride (TiN) layer (not shown), is subsequently deposited onto the titanium layer 20 via a CVD process, to form a barrier layer consisting of the titanium layer 20 and the titanium nitride layer. A metal wiring layer 22, comprised of a conductive metal, such as tungsten (W), aluminum (Al) or copper (Cu), is then deposited on the barrier layer and patterned via a photolithographic process or a chemical mechanical polishing (CMP) process to form a metal contact in contact with the heavily doped region 12, e.g., a P+ well.
Disadvantageously, since the heavily doped region 12, e.g., a P+ well, is formed using an ion-implantation process employing BF2+, dopant concentration of the interface material located between the heavily doped region 12, e.g., a P+ well, and the titanium layer 20 (i.e., the surface portion of the substrate) is reduced due to a diffusion of fluorine (F) and boron (B) caused by the thermal budget used during the formation of the titanium silicide layer. In this reaction, diffused fluorine and boron react with the titanium to form materials having high resistivity, e.g., TiBx and TiFx, thereby increasing the contact resistance in the heavily doped region 12, e.g., a P+ well. Due to fluorine diffusion, micro-voids are also created in the titanium silicide layer, which further increases the contact resistance of the heavily doped region 12, e.g., a P+ well.
In addition, if the oxide layer 18 that has grown on the exposed silicon surface is not removed before depositing the barrier layer, the formation of the metal silicide layer becomes non-uniform, which further increases the contact resistance. Thus, before depositing the refractory metal layer such as the titanium layer 20, a pre-cleaning process to remove the native oxide layer 18 should be conducted.
Typically, a pre-cleaning process is performed using wet cleaning equipment. However, when the underlying layer of a contact is comprised of a cobalt silicide (CoSi2), a plasma RF etching chamber should be added to a deposition chamber because of the wet bath contamination caused by the pre-cleaning of the barrier layer which creates additional expenses due to retrofitting and loss of process time.
Further, in a case where the titanium silicide is formed by a CVD or PE-CVD process using a TiCl4 source gas, chlorine (Cl) atoms, which are dissociated from the TiCl4 gas, remain as impurities in the titanium silicide layer, and reaction by-products of TiClx-type compounds are generated in the deposition chamber. During subsequent heating, the chlorine atoms existing at the surface of the titanium silicide layer reacts with titanium or silicon to increase the contact resistance.